1. Field of the Invention
The present invention relates to a hierarchical wafer yield prediction method and a hierarchical lifetime prediction method, and more particularly, to a hierarchical wafer yield prediction method and a hierarchical lifetime prediction method both using a yield/lifetime domain, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain as different levels for prediction.
2. Description of the Prior Art
In conventional wafer fabrication, yield of fabricated wafers is highly monitored for improvements. Moreover, the yield may be predicted by observing data generated by fault detection and classification machine sensors which are responsible for detecting defects of the fabricated wafers.
However, there are several intermediate processes in wafer fabrication, and these intermediate processes may introduce large scales of noises in yield prediction. If these intermediate processes are highly correlative, or if these intermediate processes are performed as flat algorithms, the noises in the yield prediction will get worse.